The present invention relates to an image reading apparatus using sensors closely arranged in a uniformly staggered array, and more particularly relates to a technique for improving the reading speed of such an apparatus.
Currently, for photoelectrically reading the density of an image on an original document, there exists a fine sensor in which a plurality of light receiving elements composed of, for example, amorphous silicon are aligned on a line in the transverse direction of the original document to be read. When, for example, a document of A4 size (Japanese standard) is read in its transverse direction (about 300 mm) with a resolution of 16 dots (picture elements) per mm, it is necessary to provide a line sensor having approximately 4,800 image sensing elements on a substrate of approximately 300 mm. However, it is difficult to provide so many light receiving elements on one substrate substantially uniformly and without omission. Therefore, such an arrangement is impractical from the viewpoint of cost unless yield or the like is improved.
This problem is partially solved by placing a plurality of line sensors, each having approximately 1,000 light receiving elements, on one substrate.
A line sensor, however, has invalid bits at its opposite ends, which are incapable of reading an image. Accordingly, unreadable regions are formed when a plurality of line sensors are arranged side by side in a line. This problem is partially solved by arranging a plurality of line sensors in a uniformly staggered array so that adjacent line sensors read different lines respectively.
When a plurality of line sensors are arranged in a uniformly staggered array, adjacent line sensors scan and read different surface portions of an original document. That is, if an original document and line sensors are moved in the direction perpendicular to the scanning direction of the line sensors so as to read the surface of the original document, a time lag corresponding to the positional discrepancy between line sensors adjacent to each other is produced between signals from the first row of line sensors for precedingly scanning the original document and the second row of line sensors for succeedingly scanning the same original document. For example, in a copying machine in which a high resolution of 16 picture elements per mm is required, the time lag undesirably affects the accuracy of reading. Moreover, in reading a color image, the time lag also affects color balance.
Therefore, in order to obtain a continuous signal of one line from image signals divisionally read by means of a plurality of line sensors, at least a signal output from the first row of line sensors for precedingly scanning an original document is stored and then the stored signal is read out in synchronism with an output signal succeedingly produced from the second row of line sensors. For example, assume that the quantity of the positional discrepancy is 250 .mu.m, the resolution is 16 dot/mm, and a delay of four lines is required.
The above example might use one of two systems: 1) a system in which a signal read out from the first row sensors is stored in digital form after analog-to-digital conversion and 2) a system in which a signal read out from the first row by sensors is stored in analog form before analog-to-digital conversion. Various proposals have been made in which a digital memory for correction is provided external to the sensors, and an analog memory is provided as an output delay means to delay the output data of the sensors to thereby correct the time lag (for example, Japanese unexamined Patent Publication No. 60-16760, 60-31357, 60-31358, 60-134167, 60-134168, and 61-269462).
The former system, in which the signal to be processed is a digital signal, is advantageous because the signal processing is easy and is hardly affected from the outside. However, a large memory is required to store a digital signal. For example, assuming that a digital signal has 8 bits, a line sensor has 1,000 light receiving elements, and a positional discrepancy between line sensors adjacent to each other is equal to four lines, a memory having a storage capacity of at least 8 (bits).times.1,000 (elements).times.4 (lines)=32,000 (bits) is required. In order to eliminate the need for large amounts of storage, therefore, the latter system, in which an analog signal is stored before it is converted into a digital signal, is preferable.
A line sensor shown in FIG. 7 comprises a vertical shift register including a built-in analog memory. The quantity of delay for one of 1 to 7 lines of the line sensor can be selected by changing the access conditions of seven stages of line shift gates .phi.V1 to .phi.V7. The reference symbol SH represents a shift gate. Symbols .phi.1A and .phi.2A represent first and second phase clocks, respectively. Symbol .phi.2B represents a second phase final-stage clock. Symbol RG represents a reset gate. Symbol OD represents an output transistor drain. Symbol OS represents an output transistor source, and symbol IG represents an input gate. In this line sensor, a one-line output time T.sub.exp is equivalent to the sum of a vertical register driving time T.sub.V and a horizontal register driving time T.sub.H, as shown in FIG. 8(b). The number of delay lines is controlled by the vertical register driving time T.sub.V. FIG. 8(a) shows an example of a driving signal when the number of delay lines is set to "0".
In an image reading apparatus, generally, reduction or enlargement in a main scanning direction is performed by thinning or thickening signals in a video circuit, or by similar processing, and the reduction or enlargement in a sub-scanning direction is performed by increasing or decreasing the speed of movement in the sub-scanning direction.
In existing image reading apparatus, therefore, the speed of reading (the number of read lines per unit time) is fixed, and the resolution in the sub-scanning direction is changed by changing the speed of movement in the sub-scanning direction. That is, for example, if the resolution is 16 dot/mm when the reduction/magnification factor is 100%, the following relation is established:
______________________________________ Reduction/ enlargement Speed Resolution Zigzag correction factor % fold dot/mm number of lines ______________________________________ 50 2 8 2 100 1 16 4 200 1/2 32 8 400 1/4 64 16 ______________________________________
Therefore, the resolution increases with the increase of the reduction/enlargement factor, and the number of line memories necessary for correcting the difference of, for example, 250 .mu.m between the above-mentioned uniformly staggered arrays increases.
Accordingly, it becomes impossible to realize a required delay by only the above-mentioned built-in analog memory provided in a sensor, and it becomes necessary to also use an external memory. FIG. 9 shows an example of the assignment of the quantity of delay to a built-in memory and an external memory. When such an external memory is used in addition to the analog memory, an external memory 27 is connected to the output of an A/D converter 25 provided in a preceding sensor chip 21, and a control section 28 assigns the number of delay lines (corresponding to the establishment of the reduction/enlargement factor) to a built-in memory 23 and to the external memory 27. On the other hand, the number of delay lines for a built-in memory 24 provided in a succeeding sensor chip 22 is fixed at "0". Although the number of delay lines "0" is realized by controlling the line shift gates .phi.V1 to .phi.V7 by a driving signal shown in FIG. 8(a), when the number of delay lines is increased, timing for the line shift gates .phi.V2 to .phi.V7 (excluding the line shift gage .phi.V1) is made earlier than the line shift gate .phi.V1 by an amount of time corresponding to the number of delay lines. The diagrams (a) to (f) of FIG. 10 show the timing in the cases of the number of delay lines "1" to "6," respectively.
However, with the recent price decline for memory ICs, a system for performing more delay by an external memory has become advantageous. That is, although the increased capacity of an external memory causes costs to rise, such a memory may still be advantageous because it makes the complicated switching of the quantity of delay for a built-in line memory unnecessary. In order to use this advantage, as is shown in FIG. 9(b), a driving system is employed in which the number of delay lines for a built-in memory 23 provided in a preceding sensor chip 21 is fixed at a minimum of "2". In the case shown in FIG. 9(a), in order to set the reduction/enlargement factor between 50% and 400%, the quantity of delay selected from the number of delay lines "2" to "6" is assigned to the built-in memory 23, and that selected between the number of delay lines 0 to 10 is assigned to the external memory 27. In contrast, in the example shown in FIG. 9(b), the number of delay lines of the external memory 27 is changed to between "0" and "14." In the same manner, since a variable delay in a built-in memory is unnecessary when the quantity of delay is variable in an external memory, fixing the quantities of delay for built-in memories of preceding and succeeding sensor chips at the same value "0" further simplifies the circuit. This system is only a system for realizing the correction of the uniformly staggered array when a line sensor does not have built-in memory initially. That is, the above-mentioned use of an analog memory (Japanese Unexamined Patent Publication Nos. 60-31357 and 60-31358) is becoming less desirable with the lapse of time and changes in needs.
However, when a sensor including a built-in analog memory must be used, even though an analog memory is unnecessary, it is impossible to read the sensor unless this built-in analog memory portion is controlled. This control requirement, therefore, becomes an obstacle to using the sensor.
That is, when the analog memory has a fixed delay of "0," as described above, so that the quantity of delay is varied only in the external memory, a signal shown in FIG. 8(a) is input to the line shift gates .phi.V1 to .phi.V7 and the shift gate SH. When the width of each input pulse and each pulse interval is T, a time of 16 T is necessary for all pulses to occur. If the standard value of T is 2 .mu.sec, a time of 32 .mu.sec is necessary for all pulses to occur. As is shown in FIG. 8(b), it is necessary to stop the original charge coupled device (CCD) (also referred to as a horizontal register) while driving this vertical register. The driving of the two registers must be time-divided in such a manner because an inductive noise occurs if the horizontal register is driven to read an output while the vertical register is being driven. However, the larger the ratio of the vertical register driving time T.sub.V to the horizontal register driving time T.sub.H, the more the reading efficiency deteriorates.
In an example shown in the diagrams (a) and (b) of FIG. 9, assuming that the video rate of a sensor is f (MHc), the one-line output time T.sub.exp expressed by: EQU T.sub.exp =3000.times.1/f+32 (.mu.sec).
Therefore, in the case of 16 det/mm, the reading speed v (mm/sec) is expressed by the following equation expressing the relation between the reading speed v and the video rate f: ##EQU1## FIG. 4 shows the characteristic of the vertical register driving time T.sub.V =32 .mu.sec that is obtained by plotting the result of the above-mentioned relation. FIG. 4 also shows the characteristic of the vertical register driving time T.sub.V =4 .mu.sec that is similarly obtained by the result calculated in the case where no register is built in. Although it is unnecessary even in this case to drive the line shift gates .phi.V1 to .phi.V7, the vertical register driving time T.sub.V does not become zero, since driving of the shift gate SH is necessary.
As is shown in FIG. 4, when a sensor is driven with a high video rate (so as to read at a high speed of a little less than 200 mm/sec), the influence of the vertical register driving time T.sub.V cannot be ignored.